An accelerator for Kohonen Self-Organizing Maps

In this work we are describing hardware implementation of Kohonen SelfOrganizing Map. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA (Field-Programmable Gate Array). In this article we are describing basic neurocomputer unit structure as well as linkage of these elements into neurocomputer and units participation on computation process.